1. Field of the Invention
The present invention relates to semiconductor memory chip packaging, and in particular to stacked multiple memory chip packages.
2. Discussion of the Related Art
Due to size limitations of printed circuit boards (PCB), only a finite number of packaged chips can be placed on a PCB. As the complexity of applications increases, a greater number of chips are needed on the PCB to implement the necessary functions, which would require larger size PCBs. However, it is also desirable to decrease the size of PCBs and devices containing PCBs. One method of achieving both these objectives is to increase the number of chips in a package such as by stacking the chips, without increasing the planar area of the package. Stacking the chips can result in a smaller overall package footprint. However, stacking the chips directly on top of each other has its own drawbacks. When a chip is stacked upon a base chip, the base chip can be damaged in the process. Many different types of damage can occur including damage to the leads. Furthermore, while the footprint may be reduced, the height or aspect ratio is increased with the stacked chips.